1. Field of the Invention
The present invention generally relates to integrated circuit devices formed at high integration density and, more particularly, to formation of circuits which may have widely varying current-carrying, signal propagation time and noise immunity requirements for respective circuits and/or sub-systems which may be included therein such as in dynamic random access memories (DRAMs).
2. Description of the Prior Art
Manufacture and design of integrated circuits has greatly increased in sophistication in recent years, particularly in regard to increase of integration density. Increased integration density leads to economic advantages as increased numbers of devices and circuits may be placed on a single chip and/or within a single package (which may include a plurality of chips). Performance improvements such as reduced signal propagation time and noise immunity can usually be achieved as integration density is increased due to reduction in length of signal paths, capacitance between connections and the like. This performance gain is particularly important in integrated circuits.
Integrated circuits such as dynamic random access memories (DRAMs) can have millions of similar devices on a single chip (often collectively referred to as an array or array portion of the chip design) which are controlled throughout the chip or partitions thereof by circuits such as addressing circuits, sense amplifiers and the like, generally referred to as support circuits. Unfortunately, the circuit requirements are generally different for the array and support regions of the chip and hence ideally would require different processes during manufacture.
For example, the word lines or bit lines in a functional region of the integrated circuit such as an array portion of a memory need not carry large currents but run generally parallel to each other at close spacing and cannot generally be reduced in length for a given chip or partitioning; leading to noise through capacitive coupling between them. Therefore, very thin conductors are preferred to minimize areas of the word lines opposed to each other and resulting capacitive coupling. In contrast, the conductors of another functional portion such as the support portion of the integrated circuit device may require greater current-carrying capability but may be of reduced length while switching speed may be more critical. Therefore, it is preferred to increase the thickness of such conductors in order to reduce resistance and RC time constant signal propagation delays. However, these conductors are often in the same metal level and the use of separate processes for their fabrication is complicated by at least required masking beyond the procedures involved in the plural separate processes themselves.
Therefore, such differences in conductor thickness are not trivial to obtain. Previously proposed methods add complexity to lithographic and other manufacturing processes and can adversely affect manufacturing yield. For example, narrow connections at fine pitch are often formed by so-called damascene processes in which recesses or troughs are lithographically patterned and etched into a surface and filled by deposition of a layer of conductive material such as metal over the entire surface. Planarization (e.g. by chemical-mechanical polishing (CMP)) after filling provides separation and patterning of the conductors while they are laterally supported and insulated from each other by the material defining the groove or recess. The resulting surface is also planar and thus does not complicate further lithographic processes.
While this process provides high manufacturing yield of highly robust conductor structures of a single thickness corresponding to the trough depth, different conductor depths require two or more masking and etching steps very accurately registered with each other, as disclosed in Hirofumi, Japanese Patent Application 93-242835. Registration of these steps is very difficult and expensive and very slight misregistration can greatly compromise manufacturing yield and/or circuit performance. If conductors of different cross-sectional areas are fabricated with a single thickness (e.g. either a single mask damascene process of patterned surface deposition), the width necessary to significantly reduce resistance would increase capacitance due to the increased area, limiting the gains in signal propagation speed from decreased resistance and, perhaps more importantly, would require increased chip area such that currently available lithographic processes cannot be fully exploited to increase array density and device counts. In other words, conductor width in the support region may require exceeding the device pitch in the array region to obtain discernable performance gains.
Such difficulties are not limited to damascene processes. Surface deposition and patterning yields conductors which are much less robust and uniform and which may become even more delicate and subject to shorting and metal migration (which tends to open connections in a largely unpredictable manner) if height of the conductors is increased. A second masking operation with similarly high registration accuracy (as disclosed in Nowak et al., U.S. Pat. No. 5,182,629) or selective etchback to form thin conductors using an etch stop within the connector (as disclosed in Hingarth et al., U.S. Pat. No. 5,111,276) would be necessary in any event to provide height differences. The surface connections so formed are particularly vulnerable to damage during mask or resist removal or other required processing. Further, surface conductors of differing height present severe surface topology which may complicate or compromise subsequent lithographic processes (e.g. exposure focus).
Accordingly, there is no previously known process for forming wiring of different thicknesses in a single level of a semiconductor device without greatly increasing process complexity and cost or compromising manufacturing yield, while allowing full exploitation of current skill in the lithographic art to provide increased integration density and circuit performance.